Hi I am trying to figure out - does the Flex SPI controller support simultaneous read / write?
Let me explain what I mean.
I have the device - FPGA - which once it's clocked immediately sends some data on MISO line.
Eg when I want to issue read operation on FPGA I send the following byte stream:(cmd, addr, length)
MOSI: 0x80 | 0x12 0x34 0x56 | 0x4
MISO: 0x11 | 0xXX 0xXX 0xXX | data[0]... data[3]
As you can see the 0x11 byte is pushed by the FPGA on the same clock cycle as the first byte on MOSI. This is something like a status that allows to verify the device type. The rest 3 bytes are undefined, data[0]...data[3] is actual data that was requested.
SPI mem framework that is supposed to be used with this controller does not have such a capability (as far as I know) however I am struggling to find out whether the controller itself support something like this.
Any ideas how can I achieve this?