If an interrupt service routine is large enough such that an MCU is unable to process it before another (same) interrupt happens, and the interrupt controller is non-nested, is there a maximum number of interrupts that can stay pending?. Considering an LPC2368 as an example the datasheet only lists the following
Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts
Does this mean the CPU will drop the 33rd interrupt if I keep on increasing the frequency at which interrupt occurs, and the CPU is unable to process the ISR before another interrupt happens
That isn't how a vectored controller works. A vectored controller disambiguates the source of interrupt; multiplexing multiple interrupt sources onto a single line to the CPU. Common examples of interrupt multiplexers are the intel 8259, ARM Generic Interrupt Controller (GIC), and the intel APIC.
Interrupt activation is typically defined by either an edge or bus protocol. An edge protocol means that the transition from not-asserted to asserted generates an interrupt event to the CPU. This requires very little hardware support, as the peripheral asserting the interrupt merely has to raise a pulse to the vectored interrupt controller. The downside is that edges have no memory, so you cannot realistically share an edge interrupt between multiple sources, which might require extra hardware to disambiguate the sources.
Level interrupts, by contrast, assert when the interrupt condition is valid, and de-assert when the condition is not; so multiple interrupt sources can connect to a single interrupt (logically a wired-OR), and so the interrupt will continuously affect the operating system until the condition is resolved.
Modern, large systems distinctly prefer level interrupts. Smaller systems may prefer edge interrupts to lower system cost.