I was wondering if it was possible to expand variables themselves in a Makefile. Something to this effect:
VAR1 = var1
VAR2 = var2
ALL_VARS = $(VAR*)
Using the ALL_VARS variable should result in something like:
var1 var2
Is something like this possible?
Thank you in advance
You can't do that in standard make. But if you have GNU make, and your variable names match a (make) pattern, you can use:
should get you:
although the order is not necessarily guaranteed.