I have a design in SDAccel that shows the latency as 33000 cycles and initiation interval of 8. What does this mean?
Does it mean that the output is ready after 33000 cycles? I checked the actual time it took to output (profile summary report) and it shows 319 ms. (clock is 5ns)
Latency of 33000 cycles and initiation interval of 8 cycles indicate that you have an application with lot of pipeline stages.
Yes, your output will be ready after 33000 cycles. But you can give a new input after 8 clock cycles.