I have been trying to simulate the RISCV rocket core but to no luck, I do not have a Synopsys VCS simulator and so the rocketTestHarness.v file cannot be used as is. The rocketTestHarness.v includes a vcs_main.cc file that has extern functions that use DirectC interface handles like vc_handle and vc_getScalar vc_putScalar vc_put4stVector vc_4stVectorRef. These do not work with non VCS simulators like Questasim (the one that I have been using). Is there any way which I can use to migrate the rocketTestHarness.v file from a VCS simulator to Questasim Simulator. Or is there any other way by which I can simulate the rocket core using Questasim.
I looked at this but I'am not sure how all that works. Is it not possible to simulate the rocketchip without using the riscv_fesrvr and simulate as it would work in a natural environment. I'am willing to use DPI calls if those functions in vcs_main.cc can be translated to DPI call logic.
I would really appreciate if someone could provide some assistance on this.
Thanks in advance!!
Rocket Chip is designed to run in a tethered fashion (with HTIF and FESVR). This is not a requirement for RISC-V, but a artifact of how Rocket Chip is used in prototypes for research. Work is currently underway to define a platform specification to set a standard for boot-up and such for those that want to run standalone.
As a short-term method to get started, we do recommend using the C++ emulation provided by Chisel. Porting to Questasim will involve modifying the harness. In addition to interfacing with memory, HTIF will need to be connected to FESVR. When you get this done, if you submit a clean pull request we can integrate it for others.