Is the CPU blocked while multiple DMA transfers are in progress on OMAP 4460?

Question

I want to know how exactly DMA works in the Pandaboard. I have read the TRM of OMPA4460 which is used in the Pandaboard that the DMA System can manage a total 128 requests at a time, on up to 32 logical channels, and 4 interrupt requests. When DMA is in progress, is there any chance that the CPU will be able to perform another task at a time?

Answer 1

but I want to know that when DMA is Working is there any chances to CPU of panda board will be able to do another task at a time ???

The purpose of DMA is to specifically transfer data between an I/O device and main memory. By design this is intended to relieve the CPU of performing this transfer, which is known as programmed I/O. Once the CPU has set up the DMA controller to perform this data transfer, the CPU is then free to execute instructions for any other purpose. So the answer is "yes, a 100% chance".

Since the PandaBoard's SoC has a DMA controller with multiple channels, then several I/O operations can be concurrently performed. The constraint on performance & throughput would be memory bandwidth. Note that modern CPUs tend to use less memory bandwidth (or use memory in a more bursty manner) because of instruction and data caches. Typically the CPU is given priority access to memory when both the CPU and DMA controller contend for memory.

Note that none of these characteristics are exclusive to the PandaBoard.