Is it possible to use Imperas OVP simulator for riscV with assembly code?

Question

I'm building a verification environment for a simple RiscV core design. I generated an assembly file using the UVM generator from google and I want to use it with OVPsim but it works only with .c files. Does anyone have experience with

I tried downloading and using the GNU compiler and couldn't compile it.

Link for google's env: (slide 17):

https://content.riscv.org/wp-content/uploads/2018/12/14.25-Tao-Liu-Richard-Ho-UVM-based-RISC-V-Processor-Verification-Platform.pdf

Has anyone worked with this before? is it possible to use Imperas's OVP simulator in this environment?

Answer 1

The Imperas/OVP simulator is a binary morph code engine, and has been the reference simulator as part of the Google DV flow for 2-3 years. It is agnostic in terms of what is used to generate the in memory instructions, this could have been hand assembled, assembled or compiled. The flow shown above expects an ELF file (not a C file) for loading into the simulator, but the source of that ELF can be anything, eg gcc clang The simulator will simply perform an instruction fetch from memory, expecting to get a legal binary pattern of an instruction for execution.

so in summary to your question, Is it possible to use Imperas OVP simulator for riscV with assembly code? the answer is - yes, via an ELF input.