Inquiry about AZSPWM1 Implementation on TMS320F28335 for induction machine

Question

I am currently working on implementing the AZSPWM1 (Active Zero State PWM) method on the C2000 from TI microcontroller for a spindle motor. I have been following the relevant documentation and guidelines for AZSPWM1, but I have encountered some issues with my PWM signals. They are not behaving as expected, and I am facing challenges in achieving the desired waveform.

To provide you with a better understanding of my situation, I have attached the current waveforms and the PWM settings I am using for reference. I would greatly appreciate your expertise and guidance in identifying what might be missing or incorrect in my implementation. Any insights or suggestions you can provide would be invaluable in helping me address these issues and make progress in my project.

Thank you in advance for your time and assistance. I look forward to your response and any recommendations you may have.

Regards Muhammad

PWM setting:

switch(Sector) // sector 1...6, [0,7] zero vector

    {
        case 0 :   Ta = tmax;
                   Tb = tmax;
                   Tc = tmax;
                   break;
        case 1 :
                   Ta = tcon;
                   Tb = t1 + taon;
                   Tc = taon;

                   EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET;
                   EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR;
                   EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;

                   EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;        
                   EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
                   EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;         
                   EPwm3Regs.AQCTLA.bit.CAD = AQ_SET;
                   //reverse
                   EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;   
                   EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; 
                   break;
        case 2 :
                  Ta = t2 + taon;
                  Tb = tcon;
                  Tc = taon;

                   EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET;
                   EPwm1Regs.AQCTLA.bit.ZRO = AQ_CLEAR;
                   EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET;

                   EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;       
                   EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;
                   EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;         
                   EPwm3Regs.AQCTLA.bit.CAD = AQ_SET;
                   //reverse

                   EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;         
                   EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
                   break;

EPWM register settings are as follow: /* Setup counter mode / / Master */

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;              /* Count Up/Down (Symmetric) */
EPwm1Regs.TBPHS.bit.TBPHS = TB_DISABLE;                    /* Phase is 0 */
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;                     /* Master module, Disable phase loading */
EPwm1Regs.TBCTL.bit.PRDLD = 0;                              /* Period Register is loaded from its shadow when CNTR=Zero */
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;                    /* Clock ratio to SYSCLKOUT */
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;                       /* TBCLK = SYSCLK / (HSPCLKDIV * CLKDIV) */
EPwm1Regs.TBPRD = (TBCLK/PWMCARRIER)/2; /* Set Timer Period */ //20000 (5KHz)
EPwm1Regs.TBCTR = 0;                    /* Clear Counter */
EPwm1Regs.CMPA.bit.CMPA  = (TBCLK/PWMCARRIER)/4;   /* Set Compare A value to min*/


/* Slave 1 */
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;              /* Count Up/Down (Symmetric) */
EPwm2Regs.TBPHS.bit.TBPHS = TB_DISABLE;                    /* disable*/
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;                      /* Slave module1, Enable phase loading */
EPwm2Regs.TBCTL.bit.PHSDIR = 1;                             /* Count-down on sync () */
EPwm2Regs.TBCTL.bit.PRDLD = 0;                              /* Period Register is loaded from its shadow when CNTR=Zero */
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;                    /* Clock ratio to SYSCLKOUT */
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;                       /* TBCLK = SYSCLK / (HSPCLKDIV * CLKDIV) */
EPwm2Regs.TBPRD = (TBCLK/PWMCARRIER)/2; /* Set Timer Period */
EPwm2Regs.TBCTR = 0;                    /* Clear Counter */
EPwm2Regs.CMPA.bit.CMPA  = (TBCLK/PWMCARRIER)/4;   /* Set Compare A value to min */

/* Slave 2 */
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;              /* Count Up/Down (Symmetric) */
EPwm3Regs.TBPHS.bit.TBPHS = TB_DISABLE;                    /* disable*/
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;                      /* Slave module2, Enable phase loading */
EPwm3Regs.TBCTL.bit.PHSDIR = 1;                             /* PHSDIR bit indicates the direction the time-base counter (TBCTR) will count after a synchronization */
EPwm3Regs.TBCTL.bit.PRDLD = 0;                              /* Period Register is loaded from its shadow when CNTR=Zero */
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;                    /* Clock ratio to SYSCLKOUT */
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;                       /* TBCLK = SYSCLK / (HSPCLKDIV * CLKDIV) */
EPwm3Regs.TBPRD = (TBCLK/PWMCARRIER)/2; /* Set Timer Period */
EPwm3Regs.TBCTR = 0;                    /* Clear Counter */
EPwm3Regs.CMPA.bit.CMPA  = (TBCLK/PWMCARRIER)/4;   /* Set Compare A value to min */