# infinite loop in verilog when vvp

Asked by At

This code stuck in infinite loop when I run vvp, and I do not know why.

This code is compiled without any error.

Is there anyone that can figure out why this code stuck in infinite loop?

``````module full_adder(a, b, m, s);
parameter W = 4;
output [W-1:0] s;
input [W-1:0] a, b;
input [W:0] m;

reg i;
reg [W-1:0] s_;
always @(*) begin
for (i = 0; i < W; i = i + 1) begin
if (a[i] & b[i] & m[i]) s_[i] = 1;
else if (a[i] & ~b[i] & ~m[i] | ~a[i] & b[i] & ~m[i] | ~a[i] & ~b[i] & ~m[i]) s_[i] = 1;
else s_[i] = 0;
// when 1 is odd between a, b and carry then s is 1
end
end
assign s[W-1:0] = s_[W-1:0];
endmodule

module cla_gen(C, P, G, C0);
parameter W = 4;
output [W:0] C;
input [W-1:0] P, G;
input C0;

reg [W:0] c;
reg i;
always @(*) begin
for (i = 1; i <= W; i = i + 1) begin
c[i] = G[i-1] + P[i-1] & c[i-1];
end
end
assign C = c;
endmodule

module addsub_cla(S, C, V, A, B, M);
parameter W = 4;
output [W-1:0] S;
output C, V;
input [W-1:0] A, B;
input M;

wire [W:0] carry;
cla_gen CLAGEN(.C(carry), .P(A & ~B | ~A & B), .G(A & B), .C0(M));
assign carry = M;
full_adder FA(.a(A), .b(B), .m(carry), .s(S));
assign C = carry[W];
assign V = (carry[W] != carry[W-1]) ? 1 : 0;
endmodule
``````

## 1 Answers On Best Solutions

You have coded two infinite loops. In this declaration, `i` is one bit wide:

``````reg i;
``````

So, this is an infinite loop (because `i` is always less than `W`):

``````for (i = 1; i <= W; i = i + 1) begin
``````

Surely, you meant

``````integer i;
``````

I would recommend always using an `integer` for a loop variable, rather than some other type with a more limited bit width.