I'm designing a cpu core using Xilinx axi ram IP. To speed up the simulation, I want to transplant the simulation environment to verilator. However, things went wrong when I compiled the axi_ram_sim_netlist.v file. The error output said that Cannot find file containing module: 'RAMB36E1'and RAMB36E1 seems to be primitive in vivado. Therefore, I'm looking for some methods to use Xilinx IP or primitives in verilator or there's no way to use them in verilator.
Any help would be appreciated.
I've tried searching the internet and verilator documentation, but it didn't help.
You should check this folder and include RAMB36E1.v. /tools/Xilinx/Vivado/2021.2/data/verilog/src/xeclib/ The exact location may differ according to your OS, this is the default location of Ubuntu.
However, some syntax of the primitive RTL file may not be recognized by Verilator. This is another part people want to simulate Xilinx IP with unsupported simulator need to conquer and I don't have the solution at the moment.