How to synthesize a Rocket system?

Question

I am trying to familiarize myself with the RISC-V ISA and Rocket Chip. I have set the CONFIG=DefaultSmallConfig and generated Verilog code using make verilog command in vsim directory. I have a few questions about the outputs and how to synthesize the system using Design Compiler (DC).

1. How can I remove the ports and wires that are related to debugging? I only need to synthesize the core and its peripherals, not the debugging related modules/wires.

2. Is the top-level module ExampleRocketSystem? I have to set current_design in DC and need to know what the top-level module is.

3. Other than the freechips.rocketchip.system.DefaultSmallConfig.v output file, what do I need in order to run a full DC synthesis?

4. Assuming that I use the output Verilog file and no other files for DC synthesis, I get a lot of unresolved references and registers that are removed due to being constant. What am I missing here?

Answer 1

1) Its difficult to remove the debugging ports in general and I'm not sure how to do it cleanly. Its also worth noting that if you don't include a peripheral to boot off you will want to keep the debug port to help you load test programs.

2) Yes ExampleRocketSystem is the top level module

3) You will need an implementation of the memories used in your design as well. By default you should have a *.behav_srams.v file in generated-src that have a simple verilog behavior model of rams you can include that should turn into a bunch of flip-flops in DC. If you have access to SRAMs you would likely replace these flip-flops with those.

4) You should not get unresolved references but it is reasonable to get registers being removed due to being constant.