I hope you are well.
I am starting with RISC-V, and I would like to have the BlueSpec SSITH P1 RISC-V running in my local FPGA (Arty A7 100T or ZCU102 Zynq UltraScale). Therefore, using Vivado, I connected the SSITH P1 IP Core to the following Xilinx IP Cores: Block RAM (Single Port ROM memory), UART16550, GPIO and Block RAM (Single Port Ram Memory) with the addresses 0x7000_0000, 0x6230_0000, 0x6FFF_0000 and 0xC000_0000, respectively, as defined in the SoC_Map. The image is attached.
My question is: How can I link the software to the hardware?
I want to execute a Hello program and check the string printed through the UART. Apparently, I cannot use Vitis Platform for that as it does not recognise the RISC-V processor. I generated the Hello_world.coe (loaded in the ROM IP Core) and Hello_world.elf using the RISC-V toolchain and the linker available for the Potato RISC-V bootloader example. I also appreciate any tutorial on how to run BlueSpec cores on FPGAs.
I really appreciate any help you can provide.
I used that processor while working on SSITH. We had a different wrapper for it, which is not available, but I think the open source repo is set up in a similar way.
We used riscv gdb and openocd to connect to the processor's debug interface via JTAG, and used gdb to load, run, and debug software on the processor.
You might open an issue on the Piccolo repo to get more details on any required openocd configuration scripts, etc.