How to design a Z-scale/Cortex M0-like system using Rocket Chip?

Question

I am looking for a primitive system like Z-scale or Cortex-M0 to start a research project. It looks like Z-scale is deprecated and does not comply with the latest RISC-V specifications. Is it possible to design a system like Cortex-M0 in Rocket Chip that has very primitive components and small footprint (e.g. gate count)?

I have tried Rocket Chip's DefaultSmallConfig, but it looks like this config supports relatively complicated subsystems such as division operation. What are the parameters I should consider in order to design a Z-scale-like or Cortex-M0-like core/system (e.g. no division, floating-point operations, etc.)?

Answer 1

Look at VexRiscv (https://github.com/SpinalHDL/VexRiscv), there is two small SoC demo (Briey/Murax) and this CPU is highly customisable via an plugin system.

Answer 2

Rocket chip can't generate the simplest RISC-V variants. You may find one of these alternative RISC-V implementations more suitable.

PicoRV32 is area optimized, but takes 4 cycles per instruction: https://github.com/cliffordwolf/picorv32 ORCA is written in VHDL: https://github.com/VectorBlox/orca The uRV is good enough for CERNs LHC: https://www.ohwr.org/projects/urv-core SCR1 has JTAG debug: https://github.com/syntacore/scr1

There are many more implementations out there.