How to check values of signals at all component hierarchy levels in VHDL

Question

Typically I do this with TCL and simulator commands to make sure all signals are initialized to a valid value during reset, but I want to know if there's a way to accomplish this in pure VHDL.

Here's a TCL-based example. It is very convenient to use * and foreach loops along with the find simulator command to capture all the signal names. I simply call the check_sigs procedure whenever I want to check that all signals are valid.

# List of all signals to inspect
set sig_list {
  /tb/POR
  /tb/GSM/POR_SD_0/*
  /tb/GSM/*
  /tb/GSM/CLOCK_Condition/*
  /tb/GSM/HB_Timer_Local/*
  /tb/GSM/HB_Timer_Remote/*
  /tb/GSM/HB_Monitor_Local/*
  /tb/GSM/HB_Monitor_Remote/*
}

proc check_sigs {} {
  foreach sig_set $::sig_list {
    foreach sig [find sig $sig_set] {
      if {[exa -decimal $sig] == "X" || [exa -decimal $sig] == "U"} {
        ...
        report error here, etc
        ...
      }
    }
  }
}

I know I can use hierarchical names in VHDL-2008, but it would be too burdensome to write out each signal that way.

Does anyone know of a way to do this with pure VHDL?

Answer 1

Hierarchical names is the only way to access internal signals. And there is no wildcard, so you will need to grab each one manually. Maybe you could put an assertion inside each block that has a reset? Or how about using types that do not allow 'X' or 'U' value or multiple drivers?