How expensive are IEEE 754 double operations in respect to each other on Intel I7 chips?

Question

I want an estimative of, for example, how much more expensive is a division in relation to addition, with IEEE 754 doubles on intel processors. I need that in order to estimate which operations could lead to faster performance in an specific inner loop.

Answer 1

From the Intel 64 and IA-32 Architectures Optimization Reference Manual, pages 14-14 and 14-15,

• ADDSD has a latency of 5 cycles and a throughput of 1/cycle.

• DIVSD has a latency of 62 cycles and a throughput of 1/61 cycles.

So, if your code has tough data dependency problems, addition is about 12 times faster than division. With careful optimization, however, you can make addition 61 times faster than division. Other factors will probably make the gap larger.