I come from the non-embedded software world and I think I understand the concept and use-cases of JTAG, but there are still some open questions for me. My final goal is building CI pipeline for chip firmware. The pipeline contains basically two main things: running integration tests and the ability of "memory dump" collection when firmware fails for some reason. My questions:
- Does the fact of using JTAG influence the overall performance of the chip(power consumption, task execution time, etc.)?
- Is it possible to collect memory registers state when a particular event occurs?
- Downsides of using JTAG, in general?
Generally no, but you should check your target's data sheet/reference manual for details of its particular on-chip debug implementation. In this context JTAG itself is just a definition of the communication interface to the on-chip debug.
It may depend on how you are using the JTAG. If only to program on-chip flash, then there will be no run-time impact. If using it to read memory or stream debug data while running, that may be a different matter as there may be be bus contention between the on-chip debug and the core.
That is dependent on your target's on-chip debug rather then JTAG - as I said above, that is just the communication interface, and does nor define any particular debug capability.
It often occupies multiplexed pins that are unavailable for use in the application if you use the JTAG. Some targets use alternative "single wire" interfaces, such as ARM's SWD.
If you use the on-chip debug to halt the processor, that may change your systems real-time behaviour or cause loss of data on comms links or missed asynchronous events or interrupts.