I'm learning about the ARM Socrates NIC QoS features to provide balances arbitration between two AXI Initiators created two different sized transactions.
- AXI0: 64B (awsize = 8B, awlen = 8 beats)
- AXI1: 512B (awsize = 8B, awlen = 128 beats)
I want the bandwidth (after some time) to be balanced across both Initiators. In order to pump out as much data, I believe the best QoS Feature to use is the Address Latency Regulation, ie the 512B transaction was long enough to stall the 64B so AXI0 should up its priority to get in approx 8 transactions. I know the data flow won't look exactly like this due to target resources being unavailable or NIC limiting its outstanding transactions, but is there an intuitive way I can think about tuning the FB SCALE and the FB TARGET Register to get this balance?
I've solely just adjusted the AXI0 QoS address latency registers as this is the one with the smaller transactions size, so I want to make sure the arbiter ups its QoS to give it more transactions. With the idea that only 8 transactions are needed for AXI0 compared to 1 transaction of AXI1, I kept the scaling factor at its largest value of 0x0 (2^-3) which is an increment of 256 each cycle. Then I just started playing around with the latency, at first I set it to be 'd128 as that is how many cycles the AXI1 transaction would take, but that was decreasing the internal integrator too much. I kept adjusting the number , until I got around 'd36, but again this was just trying different values to see what happened. I can't wrap my head around why this number works.