How do I calculate the FCS field in an Ethernet Frame?

Question

I see a few implementations, but I decided to look at exactly how the specification calls out the FCS for encoding.

So say my input is as follows:

dst: 0xAA AA AA AA AA AA
src: 0x55 55 55 55 55 55
len: 0x00 04
msg: 0xDE AD BE EF

concatenating this in the order that seems to be specified in the format (and the order expressed in the spec later on) seems to indicate my input is:

M(x) = 0xAA AA AA AA AA AA 55 55 55 55 55 55 00 04 DE AD BE EF

a) "The first 32 bits of the frame are complemented."

complemented first 32 MSB of M(x): 0x55 55 55 55 AA AA 55 55 55 55 55 55 00 04 DE AD BE EF

b) "The n bits of the protected fields are then considered to be the coefficients of a polynomial M(x) of degree n – 1. (The first bit of the Destination Address field corresponds to the x(n–1) term and the last bit of the MAC Client Data field (or Pad field if present) corresponds to the x0 term.)"

I did this in previous. see M(x)

c) "M(x) is multiplied by x^32 and divided by G(x), producing a remainder R(x) of degree <=31."

Some options online seem to ignore the 33rd bit to represent x^32. I am going to ignore those simplified shortcuts for this exercise since it doesn't seem to specify that in the spec. It says to multiply M(x) by x^32. So this is just padding with 32 zeroes on the LSBs. (i.e. if m(x) = 1x^3 + 1, then m(x) * x^2 = 1x^5 + 1x^2 + 0)

padded: 0x55 55 55 55 AA AA 55 55 55 55 55 55 00 04 DE AD BE EF 00 00 00 00

Next step is to divide. I am dividing the whole M(x) / G(x). Can you use XOR shifting directly? I see some binary division examples have the dividened as 101 and the divisior as 110 and the remainder is 11. Other examples explain that by converting to decimal, you cannot divide. Which one is it for terms for this standard?

My remainder result is for option 1 (using XOR without carry bit consideration, shifting, no padding) was:

0x15 30 B0 FE

d) "The coefficients of R(x) are considered to be a 32-bit sequence."

e) "The bit sequence is complemented and the result is the CRC."

CRC = 0xEA CF 4F 01

so my entire Ethernet Frame should be:

0xAA AA AA AA AA AA 55 55 55 55 55 55 00 04 DE AD BE EF EA CF 4F 01

In which my dst address is its original value.

When I check my work with an online CRC32 BZIP2 calculator, I see this result: 0xCACF4F01

Is there another option or online tool to calculate the Ethernet FCS field? (not just one of many CRC32 calculators)

What steps am I missing? Should I have padded the M(x)? Should I have complemented the 32 LSBs instead?

Update

There was an error in my CRC output in my software. It was a minor issue with copying a vector. My latest result for CRC is (before post-complement) 35 30 B0 FE.

The post-complement is: CA CF 4F 01 (matching most online CRC32 BZIP2 versions).

So my ethernet according to my programming is currently:

0xAA AA AA AA AA AA 55 55 55 55 55 55 00 04 DE AD BE EF CA CF 4F 01

Answer 1

The CRC you need is commonly available in zlib and other libraries as the standard PKZip CRC-32. It is stored in the message in little-endian order. So your frame with the CRC would be:

AA AA AA AA AA AA 55 55 55 55 55 55 00 04 DE AD BE EF B0 5C 5D 85

Here is an online calculator, where the first result listed is the usual CRC-32, 0x855D5CB0.

Here is simple example code in C for calculating that CRC (calling with NULL for mem gives the initial CRC):

unsigned long crc32iso_hdlc(unsigned long crc, void const *mem, size_t len) {
    unsigned char const *data = mem;
    if (data == NULL)
        return 0;
    crc ^= 0xffffffff;
    while (len--) {
        crc ^= *data++;
        for (unsigned k = 0; k < 8; k++)
            crc = crc & 1 ? (crc >> 1) ^ 0xedb88320 : crc >> 1;
    }
    return crc ^ 0xffffffff;
}

The 0xedb88320 constant is 0x04c11db7 reflected.

The actual code used in libraries is more complex and faster.

Here is the calculation of that same CRC (in Mathematica), using the approach described in the IEEE 802.3 document with polynomials, so you can see the correct resulting powers of x used for the remainder calculation:

If you click on the image, it will embiggen to make it easier to read the powers.

Answer 2

The confusing factor here is the 802.3 spec. It mentions that first bit is LSB (least significant bit == bit 0) only in one place, in section 3.2.3-b, and it mentions that for CRC, "the first bit of the Destination Address field corresponds to the x^(n-1) term", so each byte input to the CRC calculation is bit reflected.

Using this online calculator:

http://www.sunshine2k.de/coding/javascript/crc/crc_js.html

Select CRC-32 | CRC32, click on custom, input reflected on, result reflected off. With this data:

AA AA AA AA AA AA 55 55 55 55 55 55 00 04 DE AD BE EF

per the spec, the calculated CRC is 0x0D3ABAA1, stored and transmitted as shown:

bit 0 first                                           | bit 7 first
AA AA AA AA AA AA 55 55 55 55 55 55 00 04 DE AD BE EF | 0D 3A BA A1

To simplify the output to always transmit bit 0 first, bit reflect the CRC bytes:

bit 0 first                                           | bit 0 first
AA AA AA AA AA AA 55 55 55 55 55 55 00 04 DE AD BE EF | B0 5C 5D 85

Note that the bit 0 always first method results in transmitted bits identical to the spec.

Change result setting for the CRC calculator, input reflected on, result reflected on. With this data:

AA AA AA AA AA AA 55 55 55 55 55 55 00 04 DE AD BE EF

the calculated CRC is 0x855D5CB0, stored least significant byte first and transmitted as shown:

bit 0 first                                           | bit 0 first
AA AA AA AA AA AA 55 55 55 55 55 55 00 04 DE AD BE EF | B0 5C 5D 85

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For verifying received data, rather than compare a calculated CRC of received data versus the received CRC, the process can calculate a CRC on received data and CRC. Assuming the alternative setup where all bytes are received bit 0 first, then with this received frame or any frame without error

bit 0 first                                           | bit 0 first
AA AA AA AA AA AA 55 55 55 55 55 55 00 04 DE AD BE EF | B0 5C 5D 85

the calculated CRC will always be 0x2144DF1C. In the case of a hardware implementation, the post complement of the CRC is usually performed one bit at a time as bits are shifted out, outside of the logic used to calculate the CRC, and in this case, after receiving a frame without error, the CRC register will always contain 0xDEBB20E3 (0x2144DF1C ^ 0xFFFFFFFF). So verification is done by computing CRC on a received frame and comparing the CRC to a 32 bit constant (0x2144DF1C or 0xDEBB20E3).