a program contains 4000 instructions. The clock rate of a non pipelined processor is 100MHz and CPI is 2. find time taken by a non-pipelined processor to complete a program ,instruction latency and throughput . part(b) the above non pipeline processor has modified into pipelined processor which has 4 stages. If the data path is evenly divided among the pipeline stages and pipeline latches with 0.5ns latency. find the cycle time, instruction latency and throughput of the pipelined processor
I gained cycle time as 80 microseconds, instruction latency as 20ns and throughput as 50 ins/microseconds. How I find clock cycle time of pipeline processor?