Driving DUT using PyUVM

Question

I am trying to drive the DUT signals using PyUVM + COCOTB. But DUT signals are not getting driven from pyuvm.

I am trying to drive DUT signals from PyUVM test . Test is passing but signals are not being driven with the expected values .

Makeppfile

TOPLEVEL = ptb_dut
MODULE = base_class
TOPLEVEL_LANG = verilog

Design file

module ptb_dut(
    input clk_in,
    input [1:0] d,
     ....
     ....
);

Python test file

class base_class(uvm_test):
    async def run_phase(self):
        self.raise_objection()
        self.bfm = cocotb.top
        self.bfm.d.value = 2   ## This is not happening

Can you please help why "d" port is not updating ?