Dividing a constant by an std_logic_vector

Question

I would like to know the proper way to divide the following:

I have the following:

constant freq : integer := 50000000;
constant minute : integer := 60;
...
variable sum : std_logic_vector(31 downto 0) := (others => '0');

sum is changed within a process, many times. When I'm done changing "sum", I need to calculate: freq*minute / sum.

I can't use numeric_std, I've been asked to use only std_logic_unsigned, std_logic_arith (I know, they're no good, but bare with it).

I figured I should do the division in integers, so I tried using the following but the results are incorrect:

suminteger := conv_integer(sum);
RPM_integer := (minute * freq) / suminteger; -- result is always less than 256
RPM_int <= conv_std_logic_vector(RPM_integer,8);

Is there any way to make this calculated with the above mentioned libraries? thanks!

Answer 1

Division is a rather complex operation to perform in hardware, and would require an IP core to do it properly, even if the numerator is constant. Every FPGA vendor has division IP cores.

If you want to use your own, the restoring division algorithm is what you seek. Don't be intimidated by Wikipedia, it is quite simple for the binary case, and you should find plenty of example on the web.

Since your divisor is 32 bits and you need 8 bits of quotient, the circuit cost is 8 32-bits subtractions and muxes. You can either use a single subtractor/mux in 8 consecutive cycles, use 8 different ones in a pipeline or a combination of both. Do not try to perform division in a single clock cycle, unless your clock is very slow.