Cache Size: 4 KB By Default Line Size : 32 Bytes Address Bits division: Number of sets: Cache Size/ 2x line size (multiplying by two as we have two way set associative cache) = 4096/2x32 = 64 Sets 1- Offset Bits: As cache line size is 32 B so we have 5 Bits for offset 2- Set Index: As there are 64 sets so we have 6 bits for set index 3- Tag: Remaining 21 Bits for Tag
I want to access multiple different addresses which map to same sets in the instruction cache and when I access the third one which maps to the same set it should evict the other lines!
I have tried the following:
#Loop to repeat accesses
li x3, 0
la t0, jump_inst_set_0
la t1, jump_inst_set_1
la s1, jump_inst_set_0_1
la t2, wfi_label
jalr t0
skip_wfi:
addi s0, s0, 1
jal wfi_label
addi x3, x3, 1
li x4, 5
bne x3, x4, repeat
exit_tst
.org 0x3000
.align 2
jump_inst_set_0:
jr t1
.org 0x4000
.align 2
jump_inst_set_1:
jr s1
.org 0x5000
.align 2
jump_inst_set_0_1:
jr t2
.org 0x6000
.align 2
wfi_label:
beq s0, x0, skip_wfi
add x0, x0, x0
ret
The idea here is to set some addresses in memory that are mapping to same set as per the defined sizes and when I access those addresses I get cache conflicts!