I can't understand how the link register of the exception mode is updated during the exception. Why for the SVC, Prefetch Abort and Undefined Instruction, the LR is having PC + 4 but for the Data Abort it's having PC + 8?
I was thinking maybe the PC is sampled by the exception at the decoding stage of the pipeline but because for the Data Abort we can't confirm that we had an error until the execution stage, PC at the time of the exceution is at the address of 2 instructions ahead which is getting fetched. but for other exceptions and even branch instructions, in the decoding stage we can confirm that the PC is going to be updated so we can take a sample of PC at the decoding stage to put the sample into the LR in case the faulty or branch instruction goes to the execution stage. Am i understanding it correctly?