Concatenate values to float64 in RISC V

Question

I have 0x40347ae1 in the 0(sp) and 0x4ccccccd in the 4(sp). How to concatenate these values in RiscV32 and store it in double register, such as fa0.

I expect the value to concatenate and become like this 0x40347ae14ccccccd and store it in fa0, so that I could display it as a float number.

Answer 1

If your environment has the "D" extension, then you have 64-bit floating point registers, and the "D" instruction set.

You want the fld instruction, which will perform a 64-bit load (flw is for 32-bit load into a floating point register).

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However, if you want the result to be 0x40347ae14ccccccd, you'll need to swap the words, since as a little endian machine it will instead load 0x4ccccccd40347ae1 given your scenario of 0x40347ae1 at 0(sp) — the lower address — and 0x4ccccccd at 4(sp) — the next sequential address.

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If you're on a 64-bit RISC V machine, you can also move values from 64-bit integer registers into 64-bit floating point registers.  However, the designers have chosen to avoid partial register reads and writes, so some processor base & extension combinations have some limits.

If you're on a 32-bit machine (with the "D" extension), the only way to access all of a 64-bit float register is via memory.  This is also the case with both 32- and 64-bit machines that implement the "Q" — quad precision extension.