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Composite Files/ Component Instantiation

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I am new(ish) to VHDL. I am trying to understand how to use different component .vhd files to build a complete structure. I am working with a Digilent PmodA7, and want to have two LEDs blink alternately.

What I have tried is Inverter.vhd and LedBlink.vhd


library IEEE;
entity Inverter is
Port (
      Inv_in  : in  std_logic;
      Inv_out : out std_logic
end Inverter;
architecture Behavioral of Inverter is
    Inv_out <= not Inv_in;
end Behavioral;


library IEEE;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity LedBlink is
Port ( 
    clk: in  std_logic;
    rst: in  std_logic;
    led_0 : out std_logic;
    led_1 : out std_logic
end LedBlink;
architecture Behavioral of LedBlink 
-- Inverter.vhd
component Inverter is 
    port ( 
        Inv_in   : in std_logic;
        Inv_out  : out std_logic
end component;

constant CLK_FREQ    : integer := 12500000;
constant BLINK_FREQ  : integer := 1;
constant CNT_MAX     : integer := CLK_FREQ/BLINK_FREQ/2 - 1;
signal cnt : unsigned(24 downto 0);
signal blink_0 : std_logic := '1';
signal blink_1 : std_logic := '1';


    if (rst = '1') then
        blink_0 <= '0';
        blink_1 <= '0';        
    elsif (clk='1' and clk'event ) then
        if cnt = CNT_MAX then
            cnt <= (others => '0');          
            -- blink_1 <= blink_0;
            A1: Inverter 
                Port map ( Inv_in => blink_0, Inv_out => blink_1); 
            blink_0 <= not blink_0;                     
            cnt <= cnt + 1;
        end if; 
    end if;
end process;
led_0 <= blink_0;
led_1 <= blink_1;
end Behavioral;

To understand how to combine files, I want to replace the line blink_1 <= blink_0; with a inverter component, ie 7404, but can’t figure out how to do this. The example I am following does not use libraries, so I am most interested in that method, although how to a library to accomplish this would be helpful. What I have is:

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