I am working on an IEEE 754 16-bit adder, and I am confused at the round to nearest, ties to even logic.
The first addition which confuses me is 169.8 (0x594E) + -0.06256 (0xAC01).
After shifting and adding (subtracting), my untrimmed mantissa is calculated to be 01010011011000000000
Splitting into guard, round, and sticky bits: 0101001101 | 1 (guard) | 0 (round) | 0 (sticky)
From my understanding, since my GSR bits are 100, this is a tie, and I use the LSB of the mantissa (1) to round the final mantissa to 0101001110, resulting in a final result of 169.8 (0x594E). However, my UVM testbench and online IEEE calculators give the result as 169.6 (0x594D).
I then tested a second test case, -1.067E4 (0xF136) + 2554.0 (0x68FD).
Using the same shift and add (subtract again), my untrimmed mantissa is 11111011011000000000
Splitting again as above: 1111101101 | 1 (guard) | 0 (round) | 0 (sticky) (same as earlier)
However, this time, when I increment the fraction to 1111101110 using the same logic, this is apparently correct, with a result of -8120.0 (0xEFEE).
I feel like I am misunderstanding the logic for determining when to round to nearest even, or I am handling the rounding incorrectly.