i dont understand completely but to me it seems like there cant be a problematic/hazardous path. So its about hazards that can occur in a half-adder circuit with Inverters XORs and Ands. Cant get to create the structural term and diagram. Would really appreciate help
To my unterstanding there cant be a data hazard but a structural hazard can obviously occur due to different gatters used. but cant get an Structural KV-Diagram out of it because theres only 2 variables x and y.
All 16 cases with the POS hazards explained are shown below: