i dont understand completely but to me it seems like there cant be a problematic/hazardous path. So its about hazards that can occur in a half-adder circuit with Inverters XORs and Ands. Cant get to create the structural term and diagram. Would really appreciate help

To my unterstanding there cant be a data hazard but a structural hazard can obviously occur due to different gatters used. but cant get an Structural KV-Diagram out of it because theres only 2 variables x and y.

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Andrew On

All 16 cases with the POS hazards explained are shown below:

\a 0 1
b\
0    
1

0
00
00
0

1
10
00
not a . not b

2
01
00
a . not b

3
11
00
not b

4
00
10
not a . b

5
10
10
not a

6
01
10
a . not b + not a . b  [(a, b)]:  (1, 0) = 1 ==> (0, 1) = 1, but (0, 0) = 0 or (1, 1) = 0 could be hit during transition; SOP resolves this: not (a.b)

7
11
10
not b + not a  [(a, b)]:  (1, 0) = 1 ==> (0, 1) = 1, but (1, 1) = 0 could be hit during transition; SOP resolves this: not (a.b)

8
00
01

9
10
01
similar to 6 above

10
01
01

11
11
01
similar to 7 aove

12
00
11

13
10
11
similar to 7 aove

14
01
11
similar to 7 aove

15
11
11