cache coherence MESI protocol

920 views Asked by At

This is a bus-based shared memoty multiprocessor system with 2 CPUs, MESI (Illionois) Protocol and write-back caches. Both CPUs access the shared variables B and C. I filled out the following state caches but i'm not sure about what happens after a variable is modified..does it go back to shared state?

enter image description here

1

There are 1 answers

2
Craig S. Anderson On

When a cache line is written to, the state of the line becomes 'M'. In all other caches the state becomes 'I'.

Thus the last two lines of your table are not correct. When P1 writes C, it invalidates the line in P0. So the 'M' in the P0 cache - VarC should be an 'I'.

A line transitions from the 'M' state to the 'S' state if cache other than the one who has written the line does a read.