I was reading this informative blog post here about the booting process on x64. In what ways is the booting process on ARM different? I had a look at Raspberry pi and it seems that the GPU is what executes before control is handed over to ARM processor. Are there any similar resources you have come across for ARM processors?
1
There are 1 answers
Related Questions in ARM
- Jiobook flashing
- How to flush denormal numbers to zero for apple silicon?
- How to exploit Unified Memory in OpenCL with CL_MEM_ALLOC_HOST_PTR flag?
- ARM Assembly code is not executing in Vitis IDE
- Which version of ARM does the M1 chip run on?
- Vector by Scalar Division with -ffast-math
- Why veneer code generated by gcc for cortex-m0 seems 8-byte aligned?
- Getting almost random time stamp counter on ARM
- Portenta H7 Baremetal Development and a Little Guidance on Embedded System Learning Roadmap
- STM32 RTC3 Mixed Mode: Writing TR resets SSR
- Implementing Quick Sort Algorithm in Visual2 with armv7
- How can I create an Inline assembly command with a multi-variable register offset?
- Inquiry: ARM Compatibility for Puppeteer
- Confusion with thumb instructions while compiling recipe for cortexm4 CPU
- Difficulty understanding virtual LPIs in GICv3
Related Questions in SOC
- A FPGA Project Proposal where I can use both PS and PL
- Starting a firmware on imx7d m4 core with bootaux, on u-boot, fail when using TCM memory but not when using DDR memory
- Install SoC EDS and create .o file using Cygwin
- Assistance Needed: Trouble Running Bare-Metal Code on second core in Cyclone V SoC
- How to implement non-blocking IO input in embedded baremetal systems?
- WEC to LogRhythm
- How to send windows logs to LogRhythm DP using Microsoft Sysmon?
- LoanIO from HPS to FPGA get analog signals,cycloneVsoc dev kit,selfmade RTOS
- How to get two separate cores the same IRQ signal and let them do different work
- FPGA Parallel output timing to satisfy input timing
- Vivado verilog 1 LUT cells form a combinatorial loop
- CAN dump utility Filter and mask id
- Increasing AHB/DMA controller performance in RK3568?
- How to find BOOT-SEL GPIO PIN?
- FIFO Depth Calculation
Popular Questions
- How do I undo the most recent local commits in Git?
- How can I remove a specific item from an array in JavaScript?
- How do I delete a Git branch locally and remotely?
- Find all files containing a specific text (string) on Linux?
- How do I revert a Git repository to a previous commit?
- How do I create an HTML button that acts like a link?
- How do I check out a remote Git branch?
- How do I force "git pull" to overwrite local files?
- How do I list all files of a directory?
- How to check whether a string contains a substring in JavaScript?
- How do I redirect to another webpage?
- How can I iterate over rows in a Pandas DataFrame?
- How do I convert a String to an int in Java?
- Does Python have a string 'contains' substring method?
- How do I check if a string contains a specific word?
Trending Questions
- UIImageView Frame Doesn't Reflect Constraints
- Is it possible to use adb commands to click on a view by finding its ID?
- How to create a new web character symbol recognizable by html/javascript?
- Why isn't my CSS3 animation smooth in Google Chrome (but very smooth on other browsers)?
- Heap Gives Page Fault
- Connect ffmpeg to Visual Studio 2008
- Both Object- and ValueAnimator jumps when Duration is set above API LvL 24
- How to avoid default initialization of objects in std::vector?
- second argument of the command line arguments in a format other than char** argv or char* argv[]
- How to improve efficiency of algorithm which generates next lexicographic permutation?
- Navigating to the another actvity app getting crash in android
- How to read the particular message format in android and store in sqlite database?
- Resetting inventory status after order is cancelled
- Efficiently compute powers of X in SSE/AVX
- Insert into an external database using ajax and php : POST 500 (Internal Server Error)
Just like the x86 boot process is documented in documents available at intel.com arm boot process is documented at arm.com as is any other processor documented.
The full sized (non-cortex-m) arm cores start by executing at address zero for reset. There is one instruction location for reset, one for data abort, undefined instruction, etc. Similar to an interrupt vector table but instead of an address there is an instruction there ideally a branch.
processors historically have some non-volatile ram mapped into the boot space or vector table or whatever, then volatile ram if any elsewhere. x86 historically near the top of ram, arm at the bottom.
ARM does not make chips like intel, it designs processor cores which other folks that make chips include in their chip designs instead of having to design their own cores and maintain compilers, etc. So the chip vendor can solve the boot process in a number of ways, some have something non-volatile mapped low then after booting you can swap in ram to that address space, whatever. In the case of the Raspberry Pi chips which are made by broadcom, they have their own gpu which actually boots the chip, it eventually reads a file assumed to be the linux kernel and root file system, but doesnt have to be. It places that file in ram (by default) in the place where a linux kernel would be loaded by a bootloader like redboot or uboot, in this case by the gpu's arm loader. the gpu then places a few breadcrumbs including the reset instruction(s) required to branch into the linux kernel (generally a very trivial thing), then release reset on the arm core allowing it to boot. so basically the arm sees only ram which is kind of nice, but that is somewhat atypical for arm or other processors to do that. Normally the main processor boots from non-volatile storage (eeprom, flash, etc) and then itself loads linux or whatever and branches to it.
A number of other processor types will have an interrupt vector table, including the arm cortex-m series which are thumb instruction set only cores. they are designed to be microcontrollers and not carry as much overhead, so the first address slot is actually meant to be filled with the init value for the stack pointer, then the second is the address for reset, and then a zillion others. The hardware is designed to preserve registers for you so that you can have the address to C functions right in the table and not have to have "some assembly required" wrappers written by you or the folks that ported the toolchain to this platform. Other processor types will just have a vector table and some assembly is required to be wrapped around interrupts and such.