I'm using multiple DMA channels in an Atmel SAMD21G18A (in an Arduino MKR1000), and I'm seeing some obviously incorrect behaviour.
DMA channels 2 & 3 are servicing a SERCOM SPI channel, using single block transfers with a completion interrupt. DMA channel 0 continuously writes a sequence of values to the DAC, triggered by a TCC channel. It uses a single descriptor for the block, which chains to itself in order to run continuously at the rate determined by TCC (10us per beat, but changing this doesn't prevent the problem).
The problem I'm seeing is that after running for a variable amount of time, usually anywhere between 5 seconds to a couple of minutes, channel 0 stops - indicating no error, just TCMPL (transfer complete). If I enable the TCMPL interrupt, the interrupt is issued when the channel stops - but not before, while it's happily repeating. Wiggling GPIOs in the DMAC ISR shows that the failure always occurs just after channel 2 or 3 has completed a block transfer.
When I examine the descriptor writeback array, I find that the channel data for channel 0 has been written with the exact channel data for either channel 2 or channel 3 - which, representing a completed transfer, causes channel 0 to deactivate. None of the surrounding memory is affected, and the same problem occurs if I assign different DMA channels.
I'm aware of item 1.7.2 in the Silicon Errata, but I'm applying the specified workaround by ensuring that the channel number of the new channel enabled (i.e. channel 2 or 3) is greater than the other channel numbers (channel 0).
I assume I'm doing something else wrong - I suspect the self-chaining has something to do with it - but while I'm working up a minimal example to share, I wonder if anybody has come across a similar issue?