ARMv8 changing from el3 to el1 secure

Question

I am trying to change from el3 to el1 secure but i keep get the processor to hang somewhere. My code is running on a Cortex-A53 (raspberry pi 3). For now I can only drop from EL3 to EL2.

/* Code to try jump to EL1 secure */
MSR SCTLR_EL1, XZR

MRS X0, SCR_EL3
ORR X0, X0, #(1<<10) // RW EL1 Execution state is AArch64.
MSR SCR_EL3, x0
MOV X0, #0b00101 // DAIF=0000
MSR SPSR_EL3, X0

ADR X0, read_core
MSR ELR_EL3, X0 // EL1 code.
ERET

read_core:

/* set stack poiter */
mov sp, #0x3F000000

/* Jump to kernel main entry point */
bl  kernel_entry

Can someone point me out what can possibly be wrong in here?

Thnks in advance

Answer 1

Finally I managed to drop rpi3 to secure el1. If someone is interested check the code.

drop_el1_secure:

/* Try drop from el3 to el1 secure */

/*=============================================================*/
/*      Enable FP/SIMD at EL1                                  */
/*=============================================================*/
mov x0, #3 << 20
msr cpacr_el1, x0           /* Enable FP/SIMD at EL1 */

/*=============================================================*/
/*      Initialize sctlr_el1                                   */
/*=============================================================*/
mov x0, xzr
orr x0, x0, #(1 << 29)          /* Checking http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0500d/CIHDIEBD.html */
orr x0, x0, #(1 << 28)          /* Bits 29,28,23,22,20,11 should be 1 (res1 on documentation) */
orr x0, x0, #(1 << 23)
orr x0, x0, #(1 << 22)
orr x0, x0, #(1 << 20)
orr x0, x0, #(1 << 11)
msr sctlr_el1, x0

/*=============================================================*/
/*      Initialize scr_el3                                     */
/*=============================================================*/
mrs x0, scr_el3
orr x0, x0, #(1<<10)        /* Lower EL is 64bits */
msr scr_el3, x0

/*=============================================================*/
/*      Initialize spsr_el3                                    */
/*=============================================================*/
mov x0, xzr
mov x0, #0b00101            /* EL1 */
orr x0, x0, #(1 << 8)       /* Enable SError and External Abort. */
orr x0, x0, #(1 << 7)       /* IRQ interrupt Process state mask. */
orr x0, x0, #(1 << 6)       /* FIQ interrupt Process state mask. */
msr spsr_el3, x0

/*=============================================================*/
/*      Initialize elr_el3                                     */
/*=============================================================*/
adr x0, el1_secure
msr elr_el3, x0

eret

el1_secure:   bl call_kernel_main