ARM1176JZF-S not allowing banked register access

Question

Today I've encountered a problem while trying to access the SPSR_abt status register from supervisor mode while in a data abort exception, on ARM1176JZF-S (RPi 1's and RPi Zero W's CPU architecture). According to the Technical Reference Manual banked registers should be available in high privilege modes (of which supervisor mode is one, if I interpreted that right), but whenever I try to compile it, it just prints the following error:

Error: Banked registers are not available with this architecture. -- `mrs r2,SPSR_abt'

I'm using the arm-none-eabi-gcc arch package cross-compiler from x86 Linux, I tried using the official one from ARM's website, but that one can't even find the architecture saying:

Fatal error: invalid -march= option: `armv6kz'

I'm not quite sure, whether I misinterpreted the Technical Reference Manual thinking there were banked registers, or my code is wrong, or the ARM compiler is broken/discontinued support for the ARMv6kz architecture, but I'd really appreciate if anyone could help me with this some way.

Oh, and finally here's the code for the data abort exception handling:

.globl _data_abort_handler_entry
_data_abort_handler_entry:
    sub lr, lr, #0x8

    srsdb sp!, #OPERATING_MODE_SVC
    cpsid if, #OPERATING_MODE_SVC

    push {r0-r12}
    push {lr}

    and r1, sp, #0x4    // Aligning the stack pointer
    sub sp, sp, r1
    push {r1}

    mrc p15, 0, r0, c6, c0, 0   // Get Fault Address Registers value: the address
                                // we tried to access, but it caused a data abort
    
    mrc p15, 0, r1, c5, c0, 0   // Get the Data Fault Status Registers value:
                                // Information about the data abort (cause, etc.)
    
    mrs r2, SPSR_abt

    blx _data_abort_handler
    
    pop {r1}
    add sp, sp, r1

    pop {lr}
    pop {r0-r12}
    rfeia sp!

And here are my gcc build options:

-mcpu=arm1176jzf-s -fpic -ffreestanding -nostdlib -c -lgcc -O2

Thank you for your help!