Altera Qsys and top level entity with array of std_logic_vector

Question

I have been trying to declare my type in a separate "mytypes.vhd" file as follows:

library ieee;
use ieee.std_logic_1164.all;

package mytypes is 
   type my_bus_array_type is array (0 to 3) of std_logic_vector(7 downto 0);
end package mytypes;

and then define an entity as follows:

library ieee;
use ieee.std_logic_1164.all;

library work;
use work.mytypes.all; 

entity my_entity is
   port(
      bus_array : in my_bus_array_type;
      ...
   );
end my_entity;

Well, this is not working. When I try to add the component to my library with the Altera Qsys tool, I get the following error:

Error: Verilog HDL or VHDL XML Interface error at my_entity.vhd(41): port "bus_array" has an unsupported type File: /home/project/my_entity.vhd Line: 41

Please note that the problem is the fact that I am trying to define inside an entity an array of standard_logic_vector, i.e. a multidimensional array. This code works correctly if I define an array of std_logic instead.

Answer 1

You mentioned you're using Quartus, which can be picky about using std_logic_vectors as base types for other items.

I do what I think you're after in Quartus using subtypes:

mytypes.vhd file:

library ieee;
use ieee.std_logic_1164.all;

package mytypes is 
  subtype BYTE_T            is std_logic_vector(7 downto 0);
  type    BYTE_A            is array (natural range <>) of BYTE_T;
  type    my_bus_array_type is array (0 to 3) of BYTE_T;
end package mytypes;

my_entity.vhd file:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.mytypes.all

entity my_entity is
port ( 
  my_bus_array1 : in BYTE_A(0 to 3);
  my_bus_array2 : in my_bus_array_type;
  ...

It's up to you whether you want to define the array range in the entity (perhaps using a generic), or in your package.

Answer 2

You have to tell the compiler to use the types you created in the mytypes package:

use work.mytypes.all

entity my_entity is
port ( my_bus_array : in my_bus_array_type;
...

Answer 3

I am not an expert in VHDL but I think you have to write your code like this :

I edited : try this instead :

    package mytypes is 
     type my_bus_array_type is array (0 to 3) of std_logic_vector(7 downto 0);  
end package mytypes;

    entity my_entity is
    port ( my_bus_array : in my_bus_array_type; 
    ...);
    end my_entity

Answer 4

What you're trying to really define is a 2D array as a port. Unfortunately, QSYS does NOT support 2D arrays. No standard Qsys interfaces support anything more than a 1 dimensional port array. Hence you'd have to break the array apart in your top level entity, export the individual ports as conduits, and then reassemble them at a higher level back into an array. This is unfortunate but true.

Answer 5

I've had similar problems, and it has had to do with handling of VHDL libraries. All HDL components in Qsys will be assigned a VHDL library with the library name set to the name of the Qsys project. Packages must be accessed with library explicitly (work. in your case) and this can mess things up. That being said, usually using packages in Qsys components has worked fine for me (including accessing them with work.).

To see how Quartus assigns and compiles into libraries, check "Design units" tab in Quartus. It lists units in folders of libraries. However, I've seen that packages will not be listed here, for some reason. Also see the .qip file of your Qsys project, where you can see exactly how Quartus has assigned your HDL files into a library.

The fact that your problem doesn't appear when instantiating your code directly in the Quartus project, rather than as a Qsys component, hints of the library issue being the explanation for this.

I've only found two references on the Qsys library handling: http://www.alteraforum.com/forum/showthread.php?t=33605 http://www.alterawiki.com/wiki/New_Qsys_Issues (see section "Unavoidable design unit collisions")

(On a side note, I often use arrays of std_logic_vector in Qsys components and never experienced a problem with that.)