I'm new to functional coverage in system-verilog. I want to write a covergroup when two signal are not equal.

For example, I have two separate coverages for each signal.

    covergroup group1 @(posedge `TB_TOP.clk); 
    cpb_1 : coverpoint `TB_TOP.sig1 {
        bins r_zero = {0};
        bins r_one = {1};
    covergroup group2 @(posedge `TB_TOP.clk); 
    cpb_2 : coverpoint `TB_TOP.sig2 {
        bins r_zero = {0};
        bins r_one = {1};

Now I want to add another when sig1 not equal to sig2 at posedge of clock. Thanks

1 Answers

Arun D'souza On Best Solutions

You mean something like this?

covergroup group3 @(posedge `TB_TOP.clk);
  // coverpoint can take an expression, so provide sig1!=sig2
  cpb_3: coverpoint (`TB_TOP.sig1 != `TB_TOP.sig2) {
    // Since we only want to cover this case, sample a true value (1) only
    bins covered = {1};