In Quartus II (V15.02) while compiling (step Analysis & Synthesis) I get the the following error when I assign the port map for the qsys design in my top entity:
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Problem Details Error:
Fatal Error: Access Violation at 0000000000000000 Module: quartus_map.exeCould not obtain stack trace
Executable: quartus_map
Comment:
None
System Information
Platform: windows64
OS name: Windows 7 // I am running Win 10 64bit
OS version: 6.2
Quartus II Information
Address bits: 64
Version: 15.0.2
Build: 153
Edition: Full Version
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After I cleaned the project (Project -> Revision name: * -> OK) I get the mentioned error every time when i run Analysis & Synthesis.
My Project contains: A VHDL File An imported .qip file generated with QSYS. In QSYS i did generate a new hdl file after the first time the error showed up but.. same result. I deleted the db order too but still same result. The project worked
My Project contained (until the first time the error showed up) a Signal Tap and .sdc file and in the sdc file were following lines in it:
derive_clock_uncertainty
derive_pll_clocks
I deleted the .sdc file from my hard drive and tried again - same result
I removed the .qip file commented the port map and compiled - success
Then i generated a new HDL file in QSYS.
After this i added the .qip file in Quartus II (port map still commented) -> success
Then i uncommented the port map definitions -> error
The last few logs before the error message pops up are the following:
Info (10264): Verilog HDL Case Statement information at altera_trace_transacto_lite.v(206): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at altera_trace_transacto_lite.v(314): all case item expressions in this case statement are onehot
Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_trfabric_capture_width.sv(92): object "state_read_addr" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_trfabric_capture_width.sv(96): object "state_d1" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_trfabric_capture_width.sv(98): object "in_ready_d1" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_trfabric_capture_width.sv(117): object "b_startofpacket_wire" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_trfabric_capture_width.sv(123): object "mem_readdata0" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_trfabric_capture_width.sv(128): object "mem_readdata1" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_trfabric_capture_width.sv(133): object "mem_readdata2" assigned a value but never read
Warning (10858): Verilog HDL warning at alt_sld_fab_alt_sld_fab_trfabric_capture_width.sv(140): object state_waitrequest used but never assigned
Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_trfabric_capture_width.sv(141): object "state_waitrequest_d1" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_trfabric_capture_width.sv(144): object "out_channel" assigned a value but never read Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_trfabric_capture_width.sv(147): object "out_empty" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_trfabric_capture_width.sv(150): object "out_error" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at alt_sld_fab_alt_sld_fab_trfabric_capture_width.sv(285): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at alt_sld_fab_alt_sld_fab_trfabric_capture_width.sv(301): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at alt_sld_fab_alt_sld_fab_trfabric_capture_width.sv(317): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at alt_sld_fab_alt_sld_fab_trfabric_capture_width.sv(334): truncated value with size 32 to match size of target (1)
Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_trfabric_avalon_st_adapter_data_format_adapter_0.sv(92): object "state_read_addr" assigned a value but never read
Warning (10858): Verilog HDL warning at alt_sld_fab_alt_sld_fab_trfabric_avalon_st_adapter_data_format_adapter_0.sv(137): object state_waitrequest used but never assigned
Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_trfabric_avalon_st_adapter_data_format_adapter_0.sv(138): object "state_waitrequest_d1" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_trfabric_avalon_st_adapter_data_format_adapter_0.sv(141): object "out_channel" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_trfabric_avalon_st_adapter_data_format_adapter_0.sv(147): object "out_error" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at alt_sld_fab_alt_sld_fab_trfabric_avalon_st_adapter_data_format_adapter_0.sv(290): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at alt_sld_fab_alt_sld_fab_trfabric_avalon_st_adapter_data_format_adapter_0.sv(311): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at alt_sld_fab_alt_sld_fab_trfabric_avalon_st_adapter_data_format_adapter_0.sv(334): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at alt_sld_fab_alt_sld_fab_trfabric_avalon_st_adapter_data_format_adapter_0.sv(353): truncated value with size 32 to match size of target (2)
Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_host_link_jtag_h2t_timing.sv(82): object "in_ready" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_stfabric_mgmt_demux_port_adap.sv(74): object "out_channel" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at alt_sld_fab_alt_sld_fab_stfabric_mgmt_time_adap.sv(84): object "in_ready" assigned a value but never read
Info (12206): 2 design partitions require synthesis
Info (12213): Partition "Top" requires synthesis because the project database does not contain a post-synthesis netlist for this partition
Info (12213): Partition "sld_hub:auto_hub" requires synthesis because the project database does not contain a post-synthesis netlist for this partition
Info (12209): No design partitions will skip synthesis in the current incremental compilation
What i try to accomplish with this code is to test the 50MHz external clock which i route to the Qsys system and the 10MHz Clock from the PLL i defined in Qsys with a LED for each Signal. Here is the code from the Top Level entity:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity helloworld_lab1 is
Port (
clk_50_max10 : in std_logic; --50MHz Clock
--clk_25_max10 : in std_logic; --25MHz Clock
--clk_10_adc : in std_logic; --10MHz Clock
cpu_resetn : in std_logic; -- Button 0
user_led : out std_logic_vector (4 downto 0);
user_pb : in std_logic_vector(3 downto 0); -- Middle Buttons
);
end entity helloworld_lab1;
architecture behaviour of helloworld_lab1 is
-- Qsys Component --
component helloworld_lab is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
pio_switch_external_connection_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export
pio_led_external_connection_export : out std_logic_vector(2 downto 0); -- export
pll_clock_clk : out std_logic -- export
);
end component helloworld_lab;
Signal cycle_counter : integer range 0 to 50000000; -- 50 MHz results in 1 Second
Signal pll_cycle_counter : integer range 0 to 10000000; -- 10 MHZ results in 1 Second
Signal led_1sec : std_logic:='0'; -- Signal LED 0
Signal led_pll : std_logic :='1'; -- Signal LED 4
Signal clock_pll : std_logic; -- Port Map PLL Clock
begin
blink_led_1s : process (clk_50_max10)
begin
if (rising_edge(clk_50_max10)) then
cycle_counter <= cycle_counter+1;
if (cycle_counter>=49999999) then
cycle_counter<=0;
led_1sec<=not led_1sec;
end if;
end if;
end process blink_led_1s;
user_led(0)<=led_1sec;
-----------------------------------------------------------------------
blink_led_pll : process (clock_pll)
begin
if (rising_edge(clock_pll))then
pll_cycle_counter <= pll_cycle_counter+1;
if (pll_cycle_counter<=9999999) then
pll_cycle_counter<=0;
led_pll<=not led_pll;
end if;
end if;
end process blink_led_pll;
user_led(4) <=led_pll;
---------------------------------------------------------------------
-----------------------------------Qsys port map-----------------------------------------------
QSYS : component helloworld_lab
port map (
clk_clk => clk_50_max10,
reset_reset_n => cpu_resetn,
pio_switch_external_connection_export => user_pb(3 downto 2),
pio_led_external_connection_export => user_led(3 downto 1),
pll_clock_clk => clock_pll
);
end architecture behaviour;
And here is a screenshot of the Qsys system.
I would appreciate any help to solve this problem.