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7 TechQA 2023-08-08T09:41:14.567000How to use the command "+incdir+" in synplify script(.tcl) when one verilog file include another verilog file?
270 views
Asked by Xiuhua Yang
Why is the wired or signal type (wor) disallowed for typedefs in SystemVerilog
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Asked by Jay M
VHDL, error message; has multiple drivers
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Asked by Alessia Houston
Defining different parameter value for simulation and synthesis
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Asked by MRm
Synthesis of two simulation identical designs - with and without second if in process for SET clk
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Asked by J. Doe
Synopsys Synplify Pro synthesis failed when using "``"
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Asked by Vlad