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Should ISR be re-entrant if I provide the same ISR to multiple interrupt lines?

score 18 · Answer 1 · 2023-07-08T23:27:11.490000

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score 408 · Answer 10 · 2021-07-05T00:53:13.267000

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TechQA.

List Question

Should ISR be re-entrant if I provide the same ISR to multiple interrupt lines?

How to start secondary risc-v core in Renode emulator?

How is ARM PPI is triggered and handled by an SMP ARM system?

What is the difference between processor cores and SMP cores?

Why atomic_thread_fence need atomic operation to work correctly

Why Linux distributes threads among NUMA nodes almost equally?

Linux softirq and SMP

Send BLE raw packet through serial port

why does read barrier can causes all effects prior to storage from another cpu be perceptible?

"SMP is not supported on this platform"

Can printf() be made SMP safe?

Is memory reordering equivalent to instruction reordering?

rpi-benchmark seems to have crashed my system: SMP : failed to stop secondary CPUs after running

How to invalidate cache on mmap'ed shared memory (multi processor machine)

for_each_possible_cpu macro in vmalloc_init() function, does the code run in only one cpu? or in every cpu?

Can't find WSL kernel directory not in /usr/src and not in /lib/modules

Kinds of IPI for x86 architecture in Linux

Confusion around spin_lock_irqsave: in what nested situation is interrupt state kept?

How seastar invoke codes on different cpus?

I have a cpu cache coherency-looking problem that I can't figure out how to fix. Two cpus see different contents of the same memory

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