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Using page-table remapping to avoid data-copying during array-reallocation

score 62 · Answer 1 · 2024-03-25T05:28:30.953000

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Using page-table remapping to avoid data-copying during array-reallocation

62 views Asked by Jeremy Friesner At 25 March 2024 at 05:28

score 30 · Answer 2 · 2024-03-13T04:04:06.683000

In x86_64 architecture, if I modify a PTE in the page table, when will it be sync to TLB?

30 views Asked by ONE NO At 13 March 2024 at 04:04

score 51 · Answer 3 · 2024-03-02T19:08:24.783000

The kernel linux's lookup_address function in x86 returns NULL when debugging a specific case of Page Fault

51 views Asked by Vinicius At 02 March 2024 at 19:08

score 20 · Answer 4 · 2024-02-22T08:29:46.560000

Understanding paging and fetching instructions from memory

20 views Asked by PC Safe At 22 February 2024 at 08:29

score 41 · Answer 5 · 2024-02-12T14:38:26.967000

What is the purpose of recursive page tables?

41 views Asked by k1r1t0 At 12 February 2024 at 14:38

score 119 · Answer 6 · 2023-11-08T16:33:11.983000

does a large, overcommitted mmap create many page table entries?

119 views Asked by ajp At 08 November 2023 at 16:33

score 246 · Answer 7 · 2023-10-31T07:30:34.383000

Will an x86_64 CPU notice that a page-table entry has changed to not-present while setting the dirty flag in the PTE?

246 views Asked by wang fuqiang At 31 October 2023 at 07:30

score 127 · Answer 8 · 2023-10-21T11:05:58.343000

Let's say we have a 32-bit system, or 64-bit system, or even 128-bit system. What's the size of each page table entry?

127 views Asked by Yajax At 21 October 2023 at 11:05

score 67 · Answer 9 · 2023-10-03T07:32:27.347000

Is there any way to keep the dirty bit in x86 page tables coherent without TLB invalidates?

67 views Asked by Moonchild At 03 October 2023 at 07:32

score 79 · Answer 10 · 2023-07-28T10:31:50.273000

How Linux uses 3-level page tables for x86 CPUs with only 2-level page tables?

79 views Asked by Franks At 28 July 2023 at 10:31

score 126 · Answer 11 · 2023-06-01T09:28:18.987000

What is the reason to extend page-directory-pointer-table base address in cr3 from 20 to 27 bits in AMD64 legacy mode (PAE)?

126 views Asked by k1r1t0 At 01 June 2023 at 09:28

score 45 · Answer 12 · 2023-05-31T12:01:24.880000

Calculating total page table size of a process (with pid) in 4-level x64-64 linux machine using/proc/pid/maps and /proc/pid/pagemap

45 views Asked by aebosnak At 31 May 2023 at 12:01

score 42 · Answer 13 · 2023-05-30T12:40:00.693000

Physical pages offset check

42 views Asked by rrpp1045 At 30 May 2023 at 12:40

score 58 · Answer 14 · 2023-05-17T08:44:27.553000

Rocket Chip - Access Exception on Page Table Walk

58 views Asked by Jaypthomer At 17 May 2023 at 08:44

score 63 · Answer 15 · 2023-05-12T07:56:55.770000

Multi-level page table in OS

63 views Asked by bloomsdayforever At 12 May 2023 at 07:56

score 133 · Answer 16 · 2023-03-11T08:49:53.480000

What happens after TLB miss in x86?

133 views Asked by Hod Badihi At 11 March 2023 at 08:49

score 145 · Answer 17 · 2023-02-13T07:51:50.537000

Dumped kernel page table info missing page flag like RW or ro

145 views Asked by pulse At 13 February 2023 at 07:51

score 364 · Answer 18 · 2023-02-10T22:39:41.377000

Unable to access any addresses after enabling MMU in QEMU on arm64

364 views Asked by stefanct At 10 February 2023 at 22:39

score 345 · Answer 19 · 2022-12-14T02:13:13.323000

Difference between Intel EPT and AMD NPT

345 views Asked by zhao bao At 14 December 2022 at 02:13

score 44 · Answer 20 · 2022-11-15T15:20:15.170000

Difficulty understanding how to translate between a virutal address and physical address

44 views Asked by IronGemini At 15 November 2022 at 15:20

TechQA.

List Question

Using page-table remapping to avoid data-copying during array-reallocation

In x86_64 architecture, if I modify a PTE in the page table, when will it be sync to TLB?

The kernel linux's lookup_address function in x86 returns NULL when debugging a specific case of Page Fault

Understanding paging and fetching instructions from memory

What is the purpose of recursive page tables?

does a large, overcommitted mmap create many page table entries?

Will an x86_64 CPU notice that a page-table entry has changed to not-present while setting the dirty flag in the PTE?

Let's say we have a 32-bit system, or 64-bit system, or even 128-bit system. What's the size of each page table entry?

Is there any way to keep the dirty bit in x86 page tables coherent without TLB invalidates?

How Linux uses 3-level page tables for x86 CPUs with only 2-level page tables?

What is the reason to extend page-directory-pointer-table base address in cr3 from 20 to 27 bits in AMD64 legacy mode (PAE)?

Calculating total page table size of a process (with pid) in 4-level x64-64 linux machine using/proc/pid/maps and /proc/pid/pagemap

Physical pages offset check

Rocket Chip - Access Exception on Page Table Walk

Multi-level page table in OS

What happens after TLB miss in x86?

Dumped kernel page table info missing page flag like RW or ro

Unable to access any addresses after enabling MMU in QEMU on arm64

Difference between Intel EPT and AMD NPT

Difficulty understanding how to translate between a virutal address and physical address

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