List Question
20 TechQA 2024-03-15T15:46:53.447000What is the microcode scoreboard?
55 views
Asked by Bryce
How to get the number of instructions executed inside a virtual machine from the host?
60 views
Asked by ray
Why does it need to be divided by 9 when calculating UPI bandwidth on the Intel platform using UNC_UPI_TxL_FLITS.ALL_DATA event?
85 views
Asked by Frontier_Setter
How to count the number of data loaded into the cache but not used?
82 views
Asked by Frontier_Setter
How to count offcore PMU events on an old kernel?
116 views
Asked by Frontier_Setter
How to collect DMA events (like memory write and read) by perf tool?
36 views
Asked by Yang2157
Getting count of TLB misses that resulted in memory access in x86-64
87 views
Asked by Arun Kp
Why don’t current tools support collecting memory bandwidth usage data at process granularity?
21 views
Asked by Frontier_Setter
Is mmap() faster than read() for perf_event_open
153 views
Asked by Kron
How do different monitoring tools calculate memory bandwidth?
56 views
Asked by Frontier_Setter
Workload Memory Bandwidth Comparison Inconsistency
105 views
Asked by TheAhmad
Can rdpmc be used to read the fixed-function counters on AMD?
53 views
Asked by BeeOnRope
Measuring ITLB_FLUSH on icelake processors
38 views
Asked by CH_skar
Which instruction is recorded when an overflow of PMC occurs?
72 views
Asked by Frontier_Setter
Don't all loads result in an L1 cache hit (after the data arrives if it initially missed)?
153 views
Asked by rrpp1045
Why LLC related performance events share the same event id in perf?
59 views
Asked by Frontier_Setter
What are the complete sources of L3 misses which aren't counted by the cache-miss event on Skylake?
102 views
Asked by Frontier_Setter
CPU performance monitor counters cannot be read directly
76 views
Asked by moep0
Is it possible to sample LOAD and STORE instructions at the same time in Intel PEBS sampling?
148 views
Asked by Azad Md Abul Kalam
Perf Result Conflict During Multiplexing
116 views
Asked by TheAhmad