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using rocket chip(a library of chisel) to generate a axi4crossbar in verilog language

score 230 · Answer 1 · 2023-03-21T03:34:37.483000

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using rocket chip(a library of chisel) to generate a axi4crossbar in verilog language

230 views Asked by xlgforever At 21 March 2023 at 03:34

score 606 · Answer 2 · 2022-06-15T20:28:58.897000

Is there a way to synchronize custom interrupt signals with AXI master transactions in Vitis HLS?

606 views Asked by PhilMasteG At 15 June 2022 at 20:28

score 532 · Answer 3 · 2020-06-16T01:08:42.197000

How can AXI4 support PCIE Producer/Consumer ordering model?

532 views Asked by Zhibo Shen At 16 June 2020 at 01:08

score 940 · Answer 4 · 2018-12-26T12:06:41.827000

Vivado, Zynq, BRAM Controller, Narrow AXI burst option

940 views Asked by CJC At 26 December 2018 at 12:06

score 1735 · Answer 5 · 2018-12-26T11:58:31.433000

Xilinx, Zynq, AXI4 interconnect. What are the performance implications of configuring register slice and data fifo options?

1.7k views Asked by CJC At 26 December 2018 at 11:58

score 1425 · Answer 6 · 2018-12-26T11:48:13.807000

AXI Protocol, difference between secure and non-secure transactions

1.4k views Asked by CJC At 26 December 2018 at 11:48

score 648 · Answer 7 · 2017-08-02T20:30:24.643000

MicroBlaze AXI4 Exceptions

648 views Asked by MateoConLechuga At 02 August 2017 at 20:30

score 143 · Answer 8 · 2017-07-18T20:21:52.387000

AXI4 AxVALID high in same clock

143 views Asked by MateoConLechuga At 18 July 2017 at 20:21

score 750 · Answer 9 · 2017-07-07T03:02:22.907000

AXI4 delay transactions

750 views Asked by MateoConLechuga At 07 July 2017 at 03:02

score 1419 · Answer 10 · 2017-03-19T18:48:37.040000

AXI4-Stream Position Bytes

1.4k views Asked by sheridp At 19 March 2017 at 18:48

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List Question

using rocket chip(a library of chisel) to generate a axi4crossbar in verilog language

Is there a way to synchronize custom interrupt signals with AXI master transactions in Vitis HLS?

How can AXI4 support PCIE Producer/Consumer ordering model?

Vivado, Zynq, BRAM Controller, Narrow AXI burst option

Xilinx, Zynq, AXI4 interconnect. What are the performance implications of configuring register slice and data fifo options?

AXI Protocol, difference between secure and non-secure transactions

MicroBlaze AXI4 Exceptions

AXI4 AxVALID high in same clock

AXI4 delay transactions

AXI4-Stream Position Bytes

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